Advances in semiconductor IC (integrated circuit) chip fabrication and packaging technologies have enabled development of highly integrated semiconductor IC chips and compact chip package structures (or electronic modules). Passive components such as capacitors, resistors and inductors are fundamental circuit components that are commonly used in chip fabrication/packaging designs. In particular, inductors are typically used in analog and mixed signal chip designs for constructing various circuits such as voltage controlled oscillators (VCOs), low-noise amplifiers (LNAs), mixers, filters and other integrated circuits. Passive components such as inductors can be fabricated as off-chip or on-chip components.
By way of example, inductors components can be fabricated as off-chip components as part of a chip package or disposed at some other location (e.g., printed circuit board). In such off-chip designs, the inductors can be connected to on-chip integrated circuits through C4 contacts or other chip-package contacts such as wire bonds, etc, which can significantly increase the series resistance and degrade circuit performance. Moreover, off-chip designs may not be suitable for high-density integration designs.
Another conventional method for implementing inductors as circuit elements includes constructing inductors as part of the frontside integrated circuit. For instance, on-chip inductors can be fabricated as part of the BEOL (back-end-of-line) wiring structure, which provides interconnects between frontside integrated circuit components. The inductor coils can be patterned in the wiring metallization levels, or patterned in metallization levels that are specifically designed for inductors.
There are various disadvantages to frontside inductor designs. For example, when an inductor is formed using thin metal films of the BEOL metallization levels, the quality (Q) factor of the inductor can decrease due to higher parasitic resistance if the inductor wires are not made wide enough to minimize the resistance. Moreover, to minimize self-capacitance, the wide inductor wires must be spaced sufficient fart apart. Consequently, the increased width and spacing of the conductor wires results in an inductor structure with a relatively large footprint.
Further, the Q factor of a frontside inductor can decrease due to coupling/crosstalk with substrate devices. In particular, eddy currents may be induced between an on-chip conductor and a conductive region in the vicinity of the on-chip inductor which reduces the effective inductance and limits the Q factor of the inductor. In addition, the inductor electric field can cause current to flow in the surrounding substrate or dielectric layers leading to further resistive losses and reduction of inductor Q factor.
Various techniques have been employed to shield (e.g., ground shields/planes) or otherwise isolate (e.g., trench isolation regions) frontside inductors to reduce such coupling/crosstalk and minimize eddy current, and thus improve the Q factor for frontside inductors. The improvement of the Q factor is achieved, however, at the expense of chip real estate as the inductor wires and associated shielding and isolation components/structures can occupy a relatively large 3-D space, which limits integration density of devices on a chip.